The present disclosure relates to layout of semiconductor devices, and more particularly to techniques advantageous in miniaturization and higher speed operation of semiconductor devices.
Conventionally, semiconductor devices are implemented as various circuit units having desired functions by arranging and coupling transistors with various widths and lengths. The circuit units are called cells. A large-scale integration (LSI) is formed by combining, arranging, and coupling the cells.
In recent years, with reduction in the areas of the cells for reducing the costs of chips, not only reduction in the sizes of transistors and interconnects provided in each cell, but also arrangement of the transistors and the interconnects without wasting space have been required. This causes the following problems particularly in the layout of complicated cells such as flip-flop circuits and latch circuits.
FIG. 11 is a layout top view for forming a latch circuit cell with a small area. In FIG. 11, transistors Tn (hereinafter n is an integer) formed by gate interconnects Gn and active regions Dn forming source/drains are provided. Metal interconnects Mn for coupling the transistors Tn are formed above the transistors Tn. Power supply active regions DV0-DV1 and power supply metal interconnects MV0-MV1 for supplying source potential of the transistors Tn extend at the upper and lower end of the cell in the horizontal direction of the drawing. Also, the interconnect plugs Pn coupling the gate interconnects Gn or the active regions Dn to the metal interconnects Mn, and power supply plugs PVn for coupling the active regions DV0-DV1 to the metal interconnects MV0-MV1 are formed. In order to reduce source potential drop of the transistors Tn, the power supply plugs PVn are usually provided in plurality at equal intervals. The centers of the power supply plugs PVn are located on grid lines Ln at pitches S0 of a predetermined length. As a result, the power supply plugs of each cell can be arranged to overlap each other when a plurality of cells, of which width is defined by integral multiple of the pitch S0, are adjacent to each other from right to left or up and down, thereby densely arranging the power supply plugs without inferring each other.
Where the potential of the gate interconnects Gn is significantly different from the source potential of the transistors Tn, noise occurring in the power supply active regions DV0-DV1 or the power supply metal interconnects MV0-MV1 influences the gate interconnects Gn to cause a malfunction of the transistors. In order to reduce the problem, the distance between the interconnect plugs Pn and the power supply plugs PVn needs to be greater than the distance between the power supply plugs PVn. For example, in FIG. 11, the distance between an interconnect plug P14 and power supply plugs PV6 and PV7, the distance between an interconnect plug P24 and power supply plugs PV10 and PV11, the distance between an interconnect plug P15 and power supply plugs PV21 and PV22, and the distance between an interconnect plug P20 and power supply plugs PV23 and PV24 need to be great. Also, even where the potential of the gate interconnects Gn is not significantly different from the source potential of the transistors Tn, the distance between the interconnect plugs Pn and the power supply plugs PVn need to be great to some extent in view of a design rule and a manufacturing process. Then, however, each cell needs to extend in the vertical direction, resulting in an increase in the area of the cell.
As a measure of solving the problem, Japanese Patent Publication No. 2010-067799 teaches omitting part of power supply plugs PVn. For example, in FIG. 12, the power supply plugs PV6, PV7, PV10, PV11, and PV21-PV24 in FIG. 11 are omitted. As a result, the layout of a cell can be maintained small, while sufficiently increasing the distance between interconnect plugs Pn and the power supply plugs PVn, thereby stabilizing circuit operation. The power supply metal interconnects MV0-MV1 have lower resistance than power supply active regions DV0-DV1. Thus, substantial source potential drop occurs in a power supply active region from a transistor and a closest power supply plug. If the power supply active region is short, in other words, if the transistor is close to the power supply plug, the source potential drop is not so problematic. For example, since a power supply plug PV9 is provided, reduction in the source potential of transistors T12 and T14 are not problematic.